JMM: single-processor can also suffer from visibility problems

From time to time I get the question if single processor (uni-processor) machines also suffer from visibility and reordering issues. Well, yes they can suffer from it. First of all, instruction reordering is not limited to multi-processor machines. Single-processor machines also benefit from optimizations based on instruction reordering, and single-processors can also use low level parallelization techniques like superscalar execution that lead to an out order execution of instructions.

But what about visibility issues? Since there only is a single-processor, writes made by one thread, even though stuck in cache, will be visible to another thread because the cache is shared between threads. So it sounds plausible that no visibility problems can happen. But there is more local memory in a cpu than only caches, namely registers. If a compiler decides to replace an expensive non volatile variable by a register (optimization called ‘register allocation’), this register will be swapped in and out when a thread context switch takes place. This means that one thread never has to see the changes made by another thread because the register content will always be thread specific. You could see the register as a thread local variable. So even on a single core machine, reordering and visibility problems still can occur.

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One Response to JMM: single-processor can also suffer from visibility problems

  1. Helpful post, thanks. Didn’t really think of visibility issues as affecting single core systems but what you say makes sense.

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